This invention relates to a fabrication sequence utilizing a test structure for monitoring level-to-level misalignment of integrated circuits and, more particularly, to a test device for electrically measuring misalignment between mask levels during manufacture of an integrated circuit wafer.
As integrated circuits become increasingly complex and small in size, it is becoming more important to be able to accurately measure the misalignment between successive features defined by different mask levels during the overall fabrication sequence. An electrical test procedure for indicating misalignment between mask levels is described in "A Comparison of Electrical and Visual Alignment Test Structures for Evaluating Photomask Alignment in Integrated Circuit Manufacturing", International Electron Devices Meeting Technical Digest, Dec. 5-7, 1977, Washington, D.C., section 2.1, pages 7A-7F.
FIG. 1 of the aforecited article shows a so-called electrical alignment resistor pair. The resistor pair is implemented in a wafer during the normal fabrication sequence in which multiple circuits are being formed in the wafer at respective chip sites. Each resistor pair comprises two orthogonally disposed straight legs formed in a given level of a multi-layered structure. The legs are parallel to reference x and y directions, respectively, and are connected together. Connections are made to spaced-apart points of each leg via contact windows formed in an overlying insulating layer. A patterned conductive layer on top of the insulating layer includes conductive portions in the windows and serves to connect the spaced-apart points to respective contact pads. During testing, current is caused to flow through each two-legged resistor. In turn, the voltages appearing across two prescribed portions of each leg are measured. An electrical indication of misalignment of the contact windows in both the x and y directions can thereby be provided. Thus, for example, for an x-direction misalignment of .DELTA.x, the voltage appearing across one portion of the x-parallel leg would ideally increase by .DELTA.V relative to the perfectly aligned case and the voltage appearing across the other portion thereof would ideally decrease by .DELTA.V. Similar indications would be provided in the y-parallel leg for y-direction window misalignment.
In practice, absolutely perfect alignment is an ideal that is never achieved. The limitations of the various standard processes and equipment employed to fabricate an actual integrated circuit device mean that even when level-to-level alignment is as good as can be practically realized, tolerably small misalignment will exist. As a result, even when level-to-level alignment is achieved within prescribed limits, the test voltages respectively appearing across the two portions of an x-parallel or a y-parallel leg will typically not be exactly equal. This normal or quiescent difference in the values of the measured voltages constitutes in effect a noise signal.
To be able to reliably detect a given misalignment, it is desired that the voltage difference between the two portions of an x leg or a y leg in a test structure of the type described above be as large as possible. Thus, efforts have been directed by workers in the field at trying to increase the voltage difference that occurs in a test structure in response to a given level-to-level misalignment. It was realized that such an improved capability, if available, would increase the sensitivity of the aforedescribed testing technique for measuring misalignment in an integrated circuit fabrication process. In turn, reliable monitoring of small level-to-level misalignments provides a basis for modifying the fabrication process to achieve higher-yield and lower-cost integrated circuit devices.